1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, in particular, to a semiconductor memory circuit layout capable of reducing the number of wires on the layout of a semiconductor memory.
2. Description of the Prior Art
FIG. 1 illustrates a semiconductor memory with a conventional Lead-On-Chip(LOC) architecture which is equipped with a peripheral circuit block 10 for applying data, control signals or address signals between a plurality of memory cell arrays for storing data.
As shown therein, the peripheral circuit block 10 includes an input/output pad 15 for inputting and outputting data to be stored in memory cells, an address and control pad 14 for inputting an address signal and a control signal, an address counter 12 for counting the address signal, address counter buffers 13-L and 13-R for buffering the address signal applied from the address counter 12, and address decoders 11-L and 1 for decoding the inputted address signal.
A general synchronous semiconductor memory requires the address counter 12 for counting from a certain particular address. In order to transmit the output of the address counter 12 to the address decoders 11-L and 11-R, buffering is performed using the buffers 13-L and 13-R.
Generally, when a pad type memory with a LOC architecture is used, the address counter 12 is placed at the center of the address pad 14. This is for maintaining the setup and hold margin between an address input pad and a clock pad.
Therefore, the address counter 12 is not placed at the center of a chip, but placed at the center of the address pad 14. The output of the address counter 12 is buffered by the two address counter buffers 13-L and 13-R at the center of a chip and then transmitted to the address decoders 11-L and 11-R at the left and right sides of the chip, respectively.
Herein, the reason why the address counter buffers 13-L and 13-R are placed at the center of the chip is to transmit a counter output of the same load to the address decoders 11-L and 11-R at both sides.
Especially, as the capacity of the semiconductor memory becomes larger, the distance between the address counter 12 and the address decoders 11-L and 11-R is lengthened, so that the necessity for the address counter buffers 13-L and 13-R increases.
In the layout of the above-described semiconductor memory chip, the layout area of an unit circuit block has been a primary factor in determining the size of the entire chip in the conventional art. However, as the semiconductor memory is highly-integrated, the routing between unit circuit blocks becomes a primary factor in determining the size of the chip rather than the layout area of an unit circuit block.
However, in the case of using a conventional technique as illustrated in FIG. 1, there is a problem that since 2A.sub.N (A.sub.N number of addresses) number of wires is required at the left portion of the chip at which the output of the address counter 12 and the output of the left address counter buffer 13-L overlap and accordingly the number of wires is increased by A.sub.N compared to the right portion of the chip, the size of the chip is increased as much.